SYNCHRONOUS COUNTER

SYNCHRONOUS COUNTER

Aim: The main aim of this project is to design a Synchronous Counter.

Block Diagram:

 

DESCRIPTION: 

In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal. In practice, there are two types of counters:

• Up counters, which increase (increment) in value
• Down counters, which decrease (decrement) in value

A simple way of implementing the logic for each bit of an ascending counter  is for each bit to toggle when all of the less significant bits are at a logic high state. For example, bit 1 toggles when bit 0 is logic high; bit 2 toggles when both bit 1 and bit 0 are logic high; bit 3 toggles when bit 2, bit 1 and bit 0 are all high; and so on.

Synchronous counters can also be implemented with hardware finite state machines, which are more complex but allow for smoother, more stable transitions.

REQUIRED COMPONENTS:

• FPGA
• XILINX ISE

REQUIRED SKILL SET:

• Knowledge on Digital design.
• Knowledge on VHDL programming.