Design and Simulation of I2C Controller

Design and Simulation of I2C Controller

Abstract

The I2C bus is a popular serial, two-wire interface used in many systems because of its low overhead. The two-wire interface minimizes interconnections so ICs have fewer pins, and the number of traces required on printed circuit boards is reduced. Capable of 100 KHz operation, each device connected to the bus is software addressable by a unique address with a simple Master/Slave protocol. The I2C Controller design contains an asynchronous microcontroller interface and provides I2C Master/Slave capability. It is intended to be used with a microcontroller or microprocessor as shown in Figure 1.

The FPGA Implementation of the I2C Controller supports the following features:

• Microcontroller interface
• Master or Slave operation
• Multi-master operation
• Software selectable acknowledge bit
• Arbitration lost interrupt with automatic mode switching from Master to Slave
• Calling address identification interrupt with automatic mode switching from Master to Slave
• START and STOP signal generation/detection
• Repeated START signal generation
• Acknowledge bit generation/detection
• Bus busy detection
• 100 KHz operation.

SOFTWARE: VHDL.

DEVELOPMENT TOOLS: XILINX ISE, MODELSIM, CHIPSCOPE.

TARGET DEVICE: SPARTAN-3E DEVICE FROM XILINX.

APPLICATIONS: The I2C can be utilized for a variety of serial interface applications, I²C is appropriate for peripherals where simplicity and low manufacturing cost are more important than speed.

ADVANTAGES: I2C logic handles bytes transfer autonomously. It also keeps track of serial transfers, and a status register (i2csta) reflects the status of I2C Bus Controller and the I2C bus.