8-Bit to 9-Bit Parity Tranceiver

8-Bit to 9-Bit Parity Tranceiver

Aim: The main aim of this project is to design a circuit which appends a parity bit with 8 bit input data and implementation on FPGA Board.

Block Diagram:

                                                                                      

DESCRIPTION:

            In this project we are going to design a circuit with 2 control signals which controls the data stored in the register. The circuit functionality changes depending upon these 2 control signals. When c1 & c2 both are “00” then data should be loaded in the Register, when “01” data should be shifted left, when “10” data should be shifted Right, when “11” should remain unchanged in the register.

          This design is used in many applications like in Serial and De-serialization applications. Data storage applications.

         

         

REQUIRED COMPONENTS:

• FPGA Board
• XILINX ISE Tool

REQUIRED SKILL SET:

• Knowledge on Digital design.
• Knowledge on VHDL programming.