PARITY GENERATOR
CIRCUIT DESIGN
Aim: The main aim of
this project is to generate parity bit from given input serial bit pattern.
Block Diagram:
DESCRIPTION:
In this project we are going
to design a system for generating a parity bit according to the given input
sequence .input is given to an XOR gate and the gate output is stored in a
register for next xor operation .final output of XOR gate gives the parity bit
this logic is implemented in the FPGA.
This design is implemented using a VHDL language, by developing a state
machine for the controller.
REQUIRED SKILL SET:
- Knowledge on Digital design.
- Knowledge on VHDL programming.
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