Seconds Counter with Seven Segment Display

Seconds Counter with Seven Segment Display

Aim: The main aim of this project is to design a Seconds Counter circuit which counts seconds and implementation on FPGA Board.

Block Diagram:

                                                                                      

DESCRIPTION:

            In this project we are going to design a Seconds counter circuit which counts seconds and display the value in seven segment display output. The circuit has one enable input which triggers the circuit when enable bit is asserted then seconds counter starts counting and display the output value. Internal logic designed using Registers and adders. Design is implemented using VHDL language and verified on Xilinx FPGA using Xilinx ISE tool. The simulation is done using Modelsim simulator tool.

          Counter logic is used in many design oriented applications where there is a need of counting occurrence of input events.

         

         

REQUIRED COMPONENTS:

• FPGA Board
• XILINX ISE Tool

REQUIRED SKILL SET:

• Knowledge on Digital design.
• Knowledge on VHDL programming.