Design and Simulation of Bus Arbiter

Design and Simulation of Bus Arbiter

Aim: The main aim of this project is to design a Bus Arbiter module which supports              4 masters.

Block Diagram:

Grant3

Grant2

Grant1

Grant0

                                                                                     

DESCRIPTION:

Any system bus interface has Master Module, Slave Module and Arbiter Module. There may be multiple Masters and multiple Slaves in a Design. Master will initiates the transfers, Slave will respond according to the transfers initiated by the Master. Where as Arbiter will Grant the System Bus to the one Master at a time according to the request signals which are asserted by the Masters. Granted Master will get access to the System Bus and initiates the transfers.

In this project we are going to design a Bus Arbiter Module which supports 4 Masters. All the Masters will assert request signals to the Arbiter, but Arbiter will assert Grant signal to the Master which as highest priority.

The design is coded using VHDL language and simulated using Modelsim Simulator.

REQUIRED SKILL SET:

• Knowledge on Digital design.
• Knowledge on VHDL programming.