Implementation of Single Error Correction and Double Error Detection IP on FPGA

Implementation of Single Error Correction and Double Error Detection IP on FPGA

Abstract

To improve system reliability, a designer may wish to provide an automatic error detection and correction circuit. One such example is the data communicated from the microprocessor to peripheral memory devices. This document describes a flow-through method for doing data SECDED with a FPGA. In this design, multiple parity bits are added to the data word upon a write to memory. With multiple parity bits, both single and double data errors can be detected upon reading the word from memory and correct single data errors. The FPGA provides a 2-bit error output flag for the microprocessor to handle detected double errors.

The SECDED design described here is the combinational logic for data communication between the microprocessor and memory. The data bus from the processor is 16-bit wide data, while the data written to memory is a 22-bit data word. When data is read back from the memory device, the stored parity bits are compared with a newly created set of parity bits from the read data. The result of this comparison, called the syndrome, will indicate the incorrect bit position in a single data error.

The IP is implemented using VHDL, synthesized with Xilinx synthesizer and Simulated using Xilinx simulator, Environment used to create a project is ISE 9.2.