8-Bit to 9-Bit Parity Tranceiver

8-Bit to 9-Bit Parity Tranceiver

Aim: The main aim of this project is to design a circuit which appends a parity bit with 8 bit input data and implementation on FPGA Board.

Block Diagram:

Input 8 bit

Output 9 bit

                                                                                      

DESCRIPTION:

            In this project we are going to design a circuit which generates the parity bit with 8-Bit Input data and appends generated parity bit with 8 bit input data while data transmission and transmits 9-bit data through transceiver. The circuit is going to implement on Xilinx FPGA with Xilinx ISE tool and verifying logic with Display units.

          This Design is used in many applications where Secure data transmission is required.

         

         

REQUIRED COMPONENTS:

• FPGA Board
• XILINX ISE Tool

REQUIRED SKILL SET:

• Knowledge on Digital design.
• Knowledge on VHDL programming.