DESIGN AND SIMULATION OF CAN CONTROLLER.

DESIGN AND SIMULATION OF CAN CONTROLLER.

ABSTRACT:

In this article is present a stand-alone controller for the controller area network (CAN) protocol. The design contains all necessary features required to implement a high performance communication protocol. The CAN controller with a simple bus line connection performs all the functions of the physical and data-link layers. The application layer is provided by a microcontroller, to which the CAN controller connects through general purpose non-multiplexed parallel 8-bits bus.

The chip is going to be coded using HDL then functional simulation will be performed, then the code will be synthesized and logic simulation will be performed. Then place and route will be done and fitted on to Spartan-3E FPGA. Then timing simulation will be done to check the complete functionality and design specifications.

The complete chip functionality is going to be demonstrated on Spartan-3E FPGA.

SOFTWARE: VHDL.

DEVELOPMENT TOOLS: XILINX ISE, MODELSIM.

APPLICATIONS: The development of increasingly complex Microsystems requires the usage of a powerful field bus system for distributed real-time networks. The CAN protocol has a wide acceptance in the field of serial communication.

BLOCK DIAGRAM:

 

Design and Simulation of Bus Arbiter

Design and Simulation of Bus Arbiter

Aim: The main aim of this project is to design a Bus Arbiter module which supports              4 masters.

Block Diagram:

Grant3

Grant2

Grant1

Grant0

                                                                                     

DESCRIPTION:

Any system bus interface has Master Module, Slave Module and Arbiter Module. There may be multiple Masters and multiple Slaves in a Design. Master will initiates the transfers, Slave will respond according to the transfers initiated by the Master. Where as Arbiter will Grant the System Bus to the one Master at a time according to the request signals which are asserted by the Masters. Granted Master will get access to the System Bus and initiates the transfers.

In this project we are going to design a Bus Arbiter Module which supports 4 Masters. All the Masters will assert request signals to the Arbiter, but Arbiter will assert Grant signal to the Master which as highest priority.

The design is coded using VHDL language and simulated using Modelsim Simulator.

REQUIRED SKILL SET:

• Knowledge on Digital design.
• Knowledge on VHDL programming.

Design and Simulation of I2C Controller

Design and Simulation of I2C Controller

Abstract

The I2C bus is a popular serial, two-wire interface used in many systems because of its low overhead. The two-wire interface minimizes interconnections so ICs have fewer pins, and the number of traces required on printed circuit boards is reduced. Capable of 100 KHz operation, each device connected to the bus is software addressable by a unique address with a simple Master/Slave protocol. The I2C Controller design contains an asynchronous microcontroller interface and provides I2C Master/Slave capability. It is intended to be used with a microcontroller or microprocessor as shown in Figure 1.

The FPGA Implementation of the I2C Controller supports the following features:

• Microcontroller interface
• Master or Slave operation
• Multi-master operation
• Software selectable acknowledge bit
• Arbitration lost interrupt with automatic mode switching from Master to Slave
• Calling address identification interrupt with automatic mode switching from Master to Slave
• START and STOP signal generation/detection
• Repeated START signal generation
• Acknowledge bit generation/detection
• Bus busy detection
• 100 KHz operation.

SOFTWARE: VHDL.

DEVELOPMENT TOOLS: XILINX ISE, MODELSIM, CHIPSCOPE.

TARGET DEVICE: SPARTAN-3E DEVICE FROM XILINX.

APPLICATIONS: The I2C can be utilized for a variety of serial interface applications, I²C is appropriate for peripherals where simplicity and low manufacturing cost are more important than speed.

ADVANTAGES: I2C logic handles bytes transfer autonomously. It also keeps track of serial transfers, and a status register (i2csta) reflects the status of I2C Bus Controller and the I2C bus.

VHDL Design and Simulation of UART

VHDL Design and Simulation of UART

Abstract

The Universal Asynchronous Receiver/Transmitter (UART) controller is the key component of the serial communications subsystem of a computer. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes. Serial transmission of digital information (bits) through a single wire or other medium is much more cost effective than parallel transmission through multiple wires. A UART is used to convert the transmitted information between its sequential and parallel form at each end of the link. Each UART contains a shift register which is the fundamental method of conversion between serial and parallel forms.

The UART usually does not directly generate or receive the external signals used between different items of equipment. Typically, separate interface devices are used to convert the logic level signals of the UART to and from the external signaling levels.

An UART, universal asynchronous receiver / transmitter is responsible for performing the main task in serial communications with computers. The device changes incoming parallel information to serial data which can be sent on a communication line. A second UART can be used to receive the information. The UART performs all the tasks, timing, parity checking, etc. needed for the communication. The only extra devices attached are line driver chips capable of transforming the TTL level signals to line voltages and vice versa.

SOFTWARE: VHDL.

DEVELOPMENT TOOLS: XILINX ISE, MODELSIM.

APPLICATIONS: The UART can be utilized for a variety of serial interface applications, UART is appropriate for peripherals where simplicity and low manufacturing cost are more important than speed.