NANO SCIENTIFIC RESEARCH CENTRE PVT.LTD., AMEERPET, HYD
WWW.NANOCDAC.COM,
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VLSI 2012 IEEE :-
1. Design
of 64-Bit Low Power Parallel Prefix VLSI Adder for High Speed Arithmetic
Circuits
2. DESIGN
OF LOW POWER HIGH SPEED VLSI ADDER SUBSYSTEM
3. HICPA:
A Hybrid Low Power Adder for High-Performance Processors
4. Low-Power
and Area-Efficient Carry Select Adder
5. Design
and Implementation of Two Variable Multiplier Using KCM and Vedic Mathematics
6. Design
and Implementation of a High Performance Multiplier using HDL
7. Implementation
of Hybrid Wave-pipelined 2D DWT Using ASIC
8. DESIGN
Of LOW-POWER AND HIGH PERFORMANCE RADIX-4 MULTIPLIER
9. Design
of Plural-Multiplier Based on CORDIC Algorithm for FFT Application
10. FPGA
implementation of Binary Coded Decimal Digit Adders and Multipliers
11. High
Speed and Area Efficient Vedic Multiplier
12. High
speed Modified Booth Encoder multiplier for signed and unsigned numbers
13. High
Speed Signed Multiplier for Digital Signal Processing Applications
14. Accumulator
Based 3-Weight Pattern Generation
15. Design
of Low Power TPG Using LP-LFSR
16. Viterbi-Based
Efficient Test Data Compression
17. A
Feature-Based Robust Digital Image Watermarking Scheme
18. Digital
Image Watermarking Based on Super Resolution Image Reconstruction
19. Hardware
Implementation of a Digital Watermarking System for Video Authentication
20. Watermarking
Mobile Phone Colour Images with Reed Solomon Error Correction Code
21. Watermarking
Scheme for Copyright Protection of 3d Animated Model
22. A
Real-time Face Detection And Recognition System
23. VHDL
Implementation of UART with Status Register
24. FPGA
Based Real Time Face Detection using Adaboost and Histogram Equalization
25. An
Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform
26. VHDL
Design for Image Segmentation
using Gabor filter for Disease Detection.
VLSI 2011 IEEE:-
1. An
Efficient Implementation of Floating Point Multiplier
2. High
Speed and Low Space Complexity FPGA Based ECC Processor
3. A
blind digital watermarking algorithm based on wavelet transform
4. A
Distributed Canny Edge Detector And Its Implementation on FPGA
5. Design
and Simulation of UART Serial Communication Module Based on VHDL
6. Design
and VLSI implementation of high-performance face-detection engine for mobile
applications
7. Design
and Implementation of Area-optimized AES based on FPGA
8. Design
of Low Power And High Speed Configurable Booth Multiplier
9. Face
detection and recognition method based on skin color and depth information
10. High Speed ASIC Design of Complex Multiplier Using Vedic
Mathematics
11. A New Reversible Design of BCD Adder
12. Digital Image Authentication from JPEG Headers
13. Design and Implementation of Low Power Digital FIR Filter
based on low power multipliers and adders on xilinx FPGA
14. Parallel Architecture for Hierarchical Optical Flow
Estimation Based on FPGA
15. A Very Fast and Low Power Carry Select Adder Circuit
16. A multichannel water making scheme based on DCT-DWT
17. An Implementation of a 2D FIR Filter Using the
Signed-Digit Number System
18. Design and Characterization of Parallel Prefix Adders
using FPGAs
19. FPGA based FFT Algorithm Implementation in WiMAX
Communications System
20. FPGA Design of AES Core Architecture for Portable Hard
Disk
21. FPGA Implementation of RS232 to Universal serial bus
converter
22. Image Encryption Based On AES Key Expansion
23. Feature Extraction of Digital Aerial Images by FPGA based
implementation of edge detection algorithms
24. An Efficient Architecture Design for VGA Monitor
Controller
25. Curve Fitting Algorithm FPGA implementation
26. FPGA Implementation of AES Algorithm
27. Design of Low Power Column Bypass Multiplier using FPGA
28. Design of Serial Communication Interface Based on FPGA
29. Design and Implementation of an FPGA-based Real-Time Face
Recognition System
30. VHDL Design and FPGA Implementation of Weighted Majority
Logic Decoders
31. Low Cost Binary128 Floating-Point FMA Unit Design with
SIMD Support
32. Design Enhancement Of combinational Neural Networks using
HDL Based FPGA framework for Pattern Recognition
33. Efficient VLSI Architecture for Discrete Wavelet Transform
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