Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes

VLSI __ M.Tech/M.E IEEE Project List 2015-16

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CODE	PROJECT TITLE	YEAR
NVD-01	A Dynamically Reconfigurable Multi-ASIP Architecture for Multi standard and Multimode Turbo Decoding	2015
NVD-02	Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication	2015
NVD-03	Functional Constraint Extraction From Register Transfer Level for ATPG	2015
NVD-04	Fault Tolerant Parallel Filters Based on Error Correction Codes	2015
NVD-05	DScanPUF: A Delay-Based Physical Unclonable Function Built Into Scan Chain	2015
NVD-06	Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding	2015
NVD-07	Quantum cost realization of new reversible gates with transformation based synthesis technique	2015
NVD-08	On the Analysis of Reversible Booth’s Multiplier	2015
NVD-09	Optimized Logarithmic Barrel Shifter in Reversible Logic Synthesis	2015
NVD-10	A novel delay & Quantum Cost efficient reversible realization of 2i × j Random Access Memory	2015
NVD-11	Exploiting Same Tag Bits to Improve the Reliability of the Cache Memories	2015
NVD-12	Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems	2015
NVD-13	32 Bit×32 Bit Multi precision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler	2014(T)
NVD-14	An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator	2014(T)
NVD-15	High-Throughput    Multi    standard    Transform    Core    Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic	2014(T)
NVD-16	Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions	2014(T)
NVD-17	Area–Delay–Power Efficient Carry-Select Adder	2014(T)
NVD-18	Multifunction Residue Architectures for Cryptography	2014(T)
NVD-19	Low-Complexity  Low-Latency  Architecture  for  Matching  of  Data Encoded With Hard Systematic Error-Correcting Codes	2014(T)
NVD-20	Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems	2014(T)
NVD-21	A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes	2014
NVD-22	Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter	2014
NVD-23	Low-Power Digital Signal Processor architecture For Wireless Sensor Nodes	2014
NVD-24	Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes	2013(T)
NVD-25	Low-Power,  High-Throughput,  and  Low-Area  Adaptive  FIR Filter Based on Distributed Arithmetic	2013(T)
NVD-26	Radix-4 and radix-8 booth encoded multi-modulus multipliers	2013(T)
NVD-27	Design and Implementation of an On-Chip Permutation Network for  Multiprocessor System-On-Chip	2013(T)
NVD-28	Multi operand Redundant Adders on FPGAs	2013
NVD-29	Global built-in self-repair for 3D memories with redundancysharing  and parallel testing	2013
NVD-30	A Practical NoC Design for Parallel DES Computation	2013
NVD-31	Parallel AES Encryption Engines for Many-Core Processor Arrays	2013
NVD-32	VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog	2013
NVD-33	A VLIW Architecture for Executing Multi-Scalar/Vector Instructions on Unified Datapath	2013
NVD-34	A Novel Modulo Adder for 2n-2k- 1Residue Number System	2013(T)
NVD-35	Low-cost  FIR  filter  designs  based  on  faithfully  rounded truncated multiple constant multiplication/accumulation	2013(T)
NVD-36	Low-Power,  High-Throughput,  and  Low-Area  Adaptive  FIR Filter Based on Distributed Arithmetic	2013(T)
NVD-37	Design  and  Implementation  of  32  Bit  Unsigned  Multiplier Using CLAA and CSLA	2013
NVD-38	Enhanced Area Efficient Architecture for 128 bit Modified CSLA	2013
NVD-39	High Performance Hardware Implementation of AES Using Minimal Resources	2013
NVD-40	Implementation of I2C Master Bus Controller on FPGA	2013
NVD-41	Novel High Speed Vedic Mathematics Multiplier using Compressors	2013
NVD-42	VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog	2013
NVD-43	VLSI implementation of Fast Addition using Quaternary Signed Digit Number System	2013
NVD-44	Design of High Performance 64 bit MAC Unit	2013
NVD-45	FPGA  Architecture  for  OFDM  Software  Defined  Radio  with an optimized Direct Digital Frequency Synthesizer	2013
NVD-46	Implementation of UART with BIST Technique in FPGA	2013
NVD-47	A High Speed Binary Floating Point Multiplier Using Dadda Algorithm	2013
NVD-48	Soft-Error-Resilient  FPGAs  Using  Built-In  2-D  Hamming Product  Code	2012(T)
NVD-49	High-Speed Low-Power Viterbi Decoder Design for TCM Decoders	2012(T)
NVD-50	Product Code Schemes for Error Correction in MLC NAND Flash Memories	2012(T)
NVD-51	Low-Power and Area-Efficient Carry Select Adder	2012(T)
NVD-52	Low-Cost Binary128 Floating-Point FMA Unit Design with SIMD Support	2012(T)
NVD-53	Design  and  Implementation  of  64-Bit  Execute  Stage  for  VLIW Processor Architecture on FPGA	2012
NVD-54	Design and FPGA-based Implementation of a High Performance   32-bit DSP Processor	2012

LOW POWER PROJECTS

NVL-01	Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop	2015(T)
NVL-02	Design Methodology of Sub threshold Three-Stage CMOS OTAs Suitable for Ultra Low-Power Low-Area and High Driving Capability	2015(T)
NVL-03	Low – Power and Area- Efficient Shift Register Using Pulsed Latches	2015(T)
NVL-04	A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection	2015(T)
NVL-05	Analysis and Design of a 14.1-mW 50100-GHz Transformer-Based PLL With Embedded Phase Shifter in 65-nm CMOS	2015(T)
NVL-06	40-Gbs 0.7-V 21 MUX and 12 DEMUX with Transformer-Coupled Technique for SerDes Interface	2015(T)
NVL-07	Low Power Conditional Pulse Control with Transmission Gate Flip-Flop	2015
NVL-08	An Efficient Design Technique for Low Power Dynamic Feed through Logic with Enhanced Performance for wide fan-in gates	2015
NVL-09	Performance Analysis of CNTFET Based Digital Logic Circuits	2015
NVL-10	A 90nm Low Power OTA Using Adaptive Bias	2015
NVL-11	Implementing Low-Power Dynamic Adders in MTCMOS Technology	2015
NVL-12	Design of high speed ternary full adder and three input XOR circuits using CNTFETs	2015
NVL-13	An 8 GHz First-Order Frequency Synthesizer for Low-Power On-Chip Clock Generation	2015
NVL-14	Free class AB–AB Miller opamp with high current enhancement	2015
NVL-15	Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits	Cadence-2015
NVL-16	Ultralow-Energy Variation-Aware Design: Adder Architecture Study	Cadence-2015
NVL-17	Designing Tunable Sub threshold Logic Circuits Using Adaptive Feedback qualization	Cadence-2015
NVL-18	Quaternary Logic Lookup Table in Standard CMOS	Cadence-2015
NVL-19	14  GSps  Four-Bit  Noninterleaved  Data  Converter  Pair  in  90  nm CMOS With Built-In Eye Diagram Testability	2014(T)
NVL-20	Power Efficient Class AB Op-Amps with High and Symmetrical Slew Rate	2014(T)
NVL-21	Carbon  Nanotubes  Blowing  New  Life  Into  NP  Dynamic  CMOS Circuits	2014(T)
NVL-22	Thwarting   Scan-Based   Attacks   on   Secure-ICs   With   On-Chip Comparison	2014(T)
NVL-23	Novel Class of Energy-Efficient Very High-Speed Conditional Push–Pull Pulsed Latches	2014(T)
NVL-24	Low-Power  Pulse-Triggered  Flip-Flop  Design  Based  on  a Signal Feed-Through Scheme	2014(T)
NVL-25	Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Full Adder Circuits	2014
NVL-26	Analysis  and  Design  of  a  Low-Voltage  Low-Power  Double-Tail Comparator	2014(T)
NVL-27	Constant Delay Logic Style	2013(T)

 NOTE: PLEASE CONTACT US IF ANY ONE IS INTERESTED TO SELECT CADENCE PROJECTS